1. Field of the Invention
This invention relates to an improvement in a semiconductor integrated circuit device including bipolar and CMOS transistors fabricated on a single semiconductor substrate. Such a device is called a Bi-CMOS IC in general.
2. Description of the Prior Art
A Bi-CMOS IC has been widely used recently because it performs logic operations at a high speed with low power consumption. The Bi-CMOS IC requires, however, an element isolation technique as is employed in a bipolar IC. That is, the bipolar and MOS transistors are formed in a semiconductor layer of one conductivity type (for example, an N-type) formed on a semiconductor substrate of the other conductivity type (i.e., a P-type). More specifically, the Bi-CMOS IC includes an N-type epitaxial layer formed on a P-type substrate. The epitaxial layer is divided into a plurality of island regions by a P-type isolation region, and the bipolar transistors, in particular NPN transistors, are formed respectively in the island regions by using each island region as each collector region. In addition to the island region, N-type well regions and P-type well regions are formed selectively in the epitaxial layer. N-channel transistors are formed in the P-well regions and the P-channel transistors are formed in the P-well regions, respectively.
Although no particular isolation region is required to isolate MOS transistors from one another, the P-well regions are formed generally in contact with the substrate. For this region, each P-well region (i.e., the so-called substrate region of each N-channel MOS transistor) is supplied with the same voltage as that supplied to the substrate.
On the other hand, with requirement for high integration and high speed, each MOS transistor is required to be scaled down. The withstand voltage of each MOS transistor is lowered accordingly. Accordingly, it is desired to form each P-well region isolately from the substrate.
For this purpose, it was announced in IEEE international Solid-State Circuits Conference, Digest of Technical Papers, pp. 52-53, 1991 that an N-type buried layer was inserted between the P-well region and the substrate to electrically isolate the P-well region from the substrate.
In such a Bi-CMOS IC, however, the P-well region is required to be formed perfectly within the buried region. An extra margin for alignment between the buired region and the P-well region is thus needed, to reduce the integration density of the Bi-CMOS IC.